1. Field of the Invention
The present invention relates generally to data correlation and specifically to data correlation based on symmetrical bit patterns.
2. Description of Related Art
In the transmission of digital information, data is transmitted according to a clock signal. Since this clock signal is typically not transmitted along with the data, this clock signal must be "recovered" from and precisely aligned with the transmitted data. One technique for synchronizing the clock signal with an incoming data signal employs a conventional data correlator, as shown in FIG. 1. Correlator 10 typically operates in conjunction with a receiving unit to which the data signal is transmitted. This receiving unit has associated therewith a clock signal having a frequency f equal to the frequency of the clock signal employed in transmitting the data signal. Using a sample clock having a frequency N times greater than the predetermined frequency f, the data signal is oversampled in a conventional manner and clocked into an m-bit shift register 12. The bits stored in register 12 are compared to a predetermined bit pattern TEST stored in an m-bit register 14 using m associated conventional logical equivalency circuits 16 which may be for instance exclusive-NOR (XNOR) gates. The signal provided at the output terminal of each of logical equivalency circuits 16 is coupled to an associated input terminal of a conventional m-input adder 18. In response to the signals generated by logical equivalency circuits 16, adder 18 provides at an output terminal thereof a signal SUM indicative of the number of matches between associated bit pairs stored in shift register 12 and register 14. On each transition of the sample clock, the bits generated by oversampling the data signal are shifted one position in register 12, thereby resulting in a new value for signal SUM. This process is repeated until a peak value for signal SUM is detected, thereby indicating that a maximum correlation between an m-bit portion of the bit pattern resulting from oversampling the data signal and the m-bit pattern stored in register 14. In this manner, the center of the bit interval of the data signal may be located, thereby facilitating a precise alignment of the clock to the data signal.
Correlator 10 "looks" for a specific bit pattern in the data signal and then correlates that pattern with a predetermined pattern stored in register 14, as described above, to determine the center of the bit internal of the data signal. For example, where correlator 10 is configured to look for the bit pattern "010" in the data signal, signal TEST stored in register 14 is set equal to "0000111111110000". FIG. 2 shows a data signal DATA containing the bit pattern "0101". Signal DATA has a zero DC offset and, as a result, the "width" of the 0's and 1's in signal DATA are equal to one another, e.g., where the digital value to be represented is a "0" signal DATA is low for precisely one clock cycle and, where the digital value to be represented is a "1" signal DATA is high for precisely one clock period. Signal DATA is 8-times (8 x) oversampled to produce the bit pattern DATA.sub.8X (see FIG. 2). Thus, each "0" bit of signal DATA is associated with eight 0's in signal DATA.sub.8X and, accordingly, each "1" bit of signal DATA is associated with eight 1's in signal DATA.sub.8X. The bits of signal DATA.sub.8X are shifted into shift register 12 as described earlier.
Shift register 12 is assumed to contain in its initial state all 0's. As bits of the signal DATA.sub.8X are shifted into shift register 12, the value of signal SUM generated at the output terminal of adder 18 changes depending upon the number of bits in register 12 which match associated ones of bits stored in register 14. For instance, after one clock cycle of the sample clock, where the bit pattern contained in register 12 is equal to "1000000000000000", the value of signal SUM is equal to 7, and after two clock cycles of the sample clock, where the bit pattern contained in register 12 is equal to "1100000000000000", the value of signal SUM is equal to 6, and so on.
The values of signal SUM generated as a function of that portion of the bit pattern of signal DATA.sub.8X are shown below in Table 1. The value of signal SUM peaks at 16 for exactly one cycle of the sample clock during which the bit pattern contained in register 12 exactly matches the pattern of signal TEST stored in register 14, i.e., where the bit pattern contained in register 12 is "0000111111110000". Signal SUM is equal to 14 for exactly one cycle of the sample clock before and exactly one cycle of the sample clock after the value of signal SUM peaks at 16, where the bit patterns in register 12 are equal to "0001111111100000" and "0000011111111000", respectively. In this manner, it may be discerned that the center of the "1" bit interval of signal DATA occurs precisely during that cycle of the sample clock when that portion of the bit pattern of signal DATA.sub.8X contained in register 12 is "0000111111110000".
______________________________________ sample clock bit pattern contained in cycle register 12 value of signal SUM ______________________________________ n - 8 1111000000001111 0 n - 7 1111100000000111 2 n - 6 1111110000000011 4 n - 5 1111111000000001 6 n - 4 1111111100000000 8 n - 3 0111111110000000 10 n - 2 0011111111000000 12 n - 1 0001111111100000 14 n 0000111111110000 16 n + 1 0000011111111000 14 n + 2 0000001111111100 12 n + 3 0000000111111110 10 n + 4 0000000011111111 8 ______________________________________
The operation of correlator 10 as described above is degraded when the received data signal has a non-zero DC offset resulting from for instance noise, mismatch, or other transmission related errors. In such a case, the width of the logic high transitions (indicative of a binary one) and the width of the logic low transitions (indicative of a binary zero) of the received data signal may not be equal to one another. For example, a signal DATA' having a non-zero DC offset and its associated 8 x oversampled bit pattern DATA.sub.8X ' are shown in FIG. 3. Note that signal DATA' represents the same bit pattern as does signal DATA of FIG. 2. However, each "0" bit of signal DATA' is associated with twelve "0" bits in signal DATA.sub.8X ' and, accordingly, each "1" bit of signal DATA' is associated with four "1" bits in signal DATA.sub.8X '.
The values of signal SUM generated by correlator 10 as a function of that portion of the bit pattern of signal DATA.sub.8X ' contained in register 12 are shown below in Table 2. In this case, where the received data signal DATA' has a non-zero DC offset as described above, the maximum number of matches between bits contained register 12 and associated ones of bits stored in register 14 is twelve. Thus, the value of signal SUM peaks at twelve. However, signal SUM peaks at a value of twelve for not just one but five cycles of the sample clock. Thus, it is impossible to detect with precision the center of the bit interval of signal DATA' using correlator 10; it can only be discerned that the center of the interval occurs somewhere during those five cycles of the sample clock where the bits patterns contained in register 12 are "0000111100000000", "0000011110000000""0000001111000000", "0000000111100000", and "0000000011110000".
TABLE 2 ______________________________________ sample clock bit pattern contained in cycle register 12 value of signal SUM ______________________________________ n - 8 1100000000001111 2 n - 7 1110000000000111 2 n - 6 1111000000000011 2 n - 5 0111100000000001 5 n - 4 0011110000000000 8 n - 3 0001111000000000 10 n - 2 0000111100000000 12 n - 1 0000011110000000 12 n 0000001111000000 12 n + 1 0000000111100000 12 n + 2 0000000011110000 12 n + 3 0000000001111000 10 n + 4 0000000000111100 8 ______________________________________
Accordingly, it would be desirable to be able to precisely determine the center of a bit interval of an incoming data signal having a non-zero DC offset.